| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 5010423 | Solid-State Electronics | 2016 | 9 Pages |
â¢A circuit model of a single-energy-level trap center in FETs is proposed.â¢The proposed model is based on the Shockley-Read-Hall (SRH) statistics of the trapping process.â¢Results of three-stage isothermal pulse measurements performed on a GaN HEMT are presented.â¢These results are used to obtain the parameters of the proposed model for the device under test.
A circuit implementation of a single-energy-level trap center in an FET is presented. When included in transistor models it explains the temperature-potential-dependent time constants seen in the circuit manifestations of charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time-domain and harmonic-balance simulations. The proposed model is based on the Shockley-Read-Hall (SRH) statistics of the trapping process. The results of isothermal pulse measurements performed on a GaN HEMT are presented. These measurement allow characterizing charge trapping in isolation from the effect of self-heating. These results are used to obtain the parameters of the proposed model.
