| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 5010447 | Solid-State Electronics | 2016 | 7 Pages |
Abstract
This work addresses the effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced Fully Depleted Silicon-on-Insulator (FDSOI) technology. A systematic methodology to extract and distinguish the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the transport properties of back channel in ultra-thin heavily doped JL devices. It is demonstrated that both volume and accumulation-layer mobility values increase when the front interface is in accumulation.
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Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
Mukta Singh Parihar, Fanyu Liu, Carlos Navarro, Sylvain Barraud, Maryline Bawedin, Irina Ionica, Abhinav Kranti, Sorin Cristoloveanu,