Simplifying FPGA Implementations of BLAKE Hash Algorithm with Block Memory Resources

Malfunctions of contemporary IT systems caused by security violations are so common and frequent that in dependability analysis now they are treated in the same way as the traditional reliability theory considered “classic” failures. For this reason to improve overall system reliability today it is necessary to apply appropriate cryptographic methods. In this paper we are dealing with one class of such methods which are based on so called hash functions, considering one specific method - the BLAKE algorithm. BLAKE was developed as a candidate for the SHA-3 contest where it successfully qualified to the final round and although it eventually lost to KECCAK it is still considered as a suitable solution with good cryptographic strength and sound performance especially in software realizations. In this paper we discuss specific modification of its hardware implementations which use built-in block RAM modules available in contemporary Field Programmable Gate Arrays. The purpose of the modification is to eliminate involved distribution of message bits among the cipher rounds in order to reduce occupation of in-array resources and also to improve performance metrics. The idea is tested on 4 different architectures: the standard iterative one and three high-speed loop-unrolled organizations with 2, 4 and 5 rounds instantiated in hardware. The results found after their implementation in a popular Spartan-3 device form Xilinx are compared to parameters of analogous architectures implemented without memory so that the savings in array utilization can be compared against additional cost incurred by the RAM modules.