Article ID Journal Published Year Pages File Type
5368405 Applied Surface Science 2007 5 Pages PDF
Abstract

Polymer thin-film transistors (PTFTs) based on poly(2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene) (MEH-PPV) semiconductor are fabricated by spin-coating process and characterized. In the experiments, solution preparation, deposition and device measurements are all performed in air for large-area applications. Hysteresis effect and gate-bias stress effect are observed for the devices at room temperature. The saturation current decreases and the threshold voltage shifts toward the negative direction upon gate-bias stress, but carrier mobility hardly changes. By using quasi-static C-V analysis for MOS capacitor structure, it can be deduced that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with hole trapping within the SiO2 gate dielectric near the SiO2/MEH-PPV interface due to hot-carrier emission.

Related Topics
Physical Sciences and Engineering Chemistry Physical and Theoretical Chemistry
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