Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
5466273 | Thin Solid Films | 2017 | 5 Pages |
Abstract
Three-layer MOS structures were patterned by lithography and subjected to a sintering process in forming gas for 20Â min. The structures annealed at high temperature present a memory window in their capacitance-voltage dependencies, which means that these structures could have a possible application as gate insulators in non-volatile memory devices. The morphology of the amorphous layers was studied by atomic force microscopy and scanning electron microscopy which revealed increase of the surface roughness and modifications in the a-Si:H layer after the high temperature process.
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Physical Sciences and Engineering
Materials Science
Nanotechnology
Authors
D. Mateos, J.A. Diniz, N. Nedev, S.N.M. Munoz, M. Curiel, M. Mederos, B. Valdez, G. Montero,