A simple analytical model of single-event upsets in bulk CMOS

This work presents an alternative approach to estimating SEU cross-section as a function of linear energy transfer (LET) that can be further developed into a method of SEU rate prediction. The goal is to propose a simple, yet physics-based, approach with just two parameters that can be used even in situations when only a process node of the device is known. The developed approach is based on geometrical interpretation of SEU cross-section and an analytical solution to the diffusion problem obtained for a simplified IC topology model. A good fit of the model to the experimental data encompassing 7 generations of SRAMs is demonstrated.