Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6617832 | Electrochimica Acta | 2013 | 7 Pages |
Abstract
The wafer scale plating uniformity with thin Cu seed layer was studied. Plating experiments were performed on 300Â mm diameter wafers with 4Â nm, 5Â nm and 10Â nm thin Cu seed layers. The plating current distribution can be very nonuniform due to the high substrate resistance. In the case of extremely thin seed layer, the corrosion of Cu due to dissolved oxygen becomes significant. It may lead to exposed barrier layer near the wafer center. A modeling methodology was developed to study the Cu plating uniformity on the wafer scale. Simulation result matches well with experimental measurement and theoretical prediction. The plating uniformity and seed layer corrosion were studied for various seed layer thicknesses using the proposed modeling approach.
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Physical Sciences and Engineering
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Chemical Engineering (General)
Authors
Liu Yang, Tanya Atanasova, Aleksandar Radisic, Johan Deconinck, Alan C. West, Philippe Vereecken,