Design architecture of simplified core protection calculator system algorithm

The methodology which simplified the Core Protection Calculator System (CPCS) architecture was developed in this work. The current CPCS implemented on Programmable Logic Controller (PLC) has been reported a lot of disadvantages such as unintended reactor trip initiation, safety channel communication disruption, and the possibility of the Common Cause Failure (CCF). This work aimed to minimize the complexity of the current system by introducing system engineering methodology to the current CPCS calculation algorithm. To verify the feasibility of CPCS calculation algorithms on FPGA that does not feature calculations, the simplified LPD calculation algorithm has been implemented in this work. The simplified LPD calculation algorithm that replaced current algorithm has been developed by adjusting the input parameters. In addition, the new approach to minimize the possibility of CCF using FPGA based architecture was also discussed in this work. Based on the functional design, the enhanced functional flow block diagram was designed and the timing simulation was performed to demonstrate the reduction of system complexity. To solve the CCF problem of CPCS, the proposed CPCS LPD calculation algorithm was converted into VHDL code, and the simplified LPD calculation algorithm was implemented in the FPGA board. The verification test was performed using LPD calculation algorithm which was a crucial part of development. The performance of the implemented system showed consistent output to the expected results.