An Improved Low-cost Adaptive Bicubic Interpolation Arithmetic and VLSI Implementation

A novel scaling algorithm is proposed which consists of a bicubic interpolation and an adaptive sharpening filter. The proposed sharpening filter is added to mitigate the blurring effects existing in bicubic interpolation methods. We also verify the scaling quality by taking into account the adaptive technique. Furthermore, we present both the procedures of filtering before and after interpolation in order to reduce the overall computing time. Compared with the previous reported techniques, our method performs better in terms of both quantitative evaluation and visual quality. To achieve the goal of real time and low cost, we describe a pipelined very large scale integration (VLSI) architecture for the implementation of the algorithm. The VLSI architecture of our image scaling processor contains 695 LEs and yields a processing rate of about 165 MHz by using field-programmable gate array (FPGA) technology. Our proposed architecture reduces the amount of gates by 36.8% while achieves an average PSNR increase of 1.5 dB in image quality.