Study of high-tech process furnace using inherently safer design strategies (IV). Advanced NAND device design and thin film process adjustment

According to perspective of process design, using inherently safer design (ISD) strategies could obtain relatively safe levels, while meeting the existing product specification requirements. The experiences for semiconductor manufacturing processes in Taiwan were planning and completed civil construction first, and then followed regulatory limits to provide the maximum piping and equipment for process production line installed in facility area, unlike the general petrochemical industry planning program considerations, indeed often ignored safety consideration. The proposed configuration was the first time applied in NAND (abbreviation of Not AND) flash component technology. There have been no similar schemes used before as in this study, and also the industry has little exploration in this way. It is an important outcome of this study. In this study case, silane (SiH4) was changed to Tetraethyl Orthosilicate (TEOS) for the process to fit ISD substitution strategy of the overall wafer products, under product specification requirements, the more hazardous gaseous silane was replaced by liquid TEOS, thus, even if both have potential hazards of fire, explosion, and poisoning, as the liquid is less likely than gas to leak or diffuse, the potential hazards are reduced, rendering it inherently safer. In this study the potential hazards scenario of 22 nm NAND Flash were analyzed first, then established process design proposal of 22 nm NAND Flash; the design proposal was created according to the above potential hazard analysis results, then process design proposal simulation and verification were presented, followed by process design proposal experiment and verification in 12″ tube, 16 batches of 22 nm NAND Flash. There are 25 wafers per batch, and 16 batches of wafer cassettes tested according to the simulation results. The experiment result showed that the product yield increased from 83.88% of SiH4 to 84.25% of TEOS, which was good because the wafer surface defect is well controlled and the various processes have no significant deviation; the direct current (DC) property improvement was increased from 6.16% to 6.76%, which might be due to the more dense liquid reaction with TEOS. In addition, the frequency response improvement increased from 4.97% to 5.16%, due to the dense material related. Finally, the peeling ability improvement also increased from 4.27% to 4.36%, as the TEOS liquid reaction was. The proposed process design improvement, as created in this study, could meet the expected process goals.