Robust space vector modulation technique for unbalance voltage disturbances

Space vector modulation (SVM) is one of the most popular PWM techniques used in multilevel inverters. The calculation of reference vector location is very important for SVM technique to obtain exact switching times and to determine correct space vectors. Balanced/unbalanced voltage disturbance occurred in a three-phase system affects the switching times and output voltage of the multilevel inverter. In this study, effects of the disturbances such as line–line faults, balanced and unbalanced voltage sags/swells to SVM technique are investigated and a new technique derived from Clarke transformation is proposed. The effects of disturbances are minimized with this new method. Power System Computer-Aided Design is used to simulate the proposed test system.