The Dynamic Properties Investigation of the PLC CPU Implemented in FPGA

The paper presents some program examples written and tested to show possibilities of construction of CPUs for PLCs build based on FPGA development platform. Presented unit is optimised for minimum response and throughput time. The constructions are based on bit-word structures of CPU and two types of data (condition) exchange methods: with acknowledge and without acknowledge – in both cases control data are passed through the set of flip-flops. Third unit is built to compare with these two. This unit is simple one processor unit which can execute both - binary and numerical operations. The experiments shown high performances of elaborated CPUs.