Multi-Processor System-on-Chip Power Estimation Model At the CABA Level

This paper examines an approach for estimating energy consumption during the HW/SW Codesign of an embedded system. Our contribution consists on the design and the development of an energy consumption model for Multi-Processor System on Chip (MPSoC). The consumption models are integrated into System on Chip Library (SoCLib) hardware components for system co-simulation at the Cycle-Accurate Bit-Accurate (CABA) level. Experimental results show the usefulness of our model to achieve correct energy estimation for MPSoC architectures with an acceptable speed of simulations.