| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 709764 | IFAC Proceedings Volumes | 2012 | 6 Pages |
Abstract
In this paper, we consider a problem of VLSI (very large scale integrated) design occurring in the routing phase. The problem is to determine the optimal size selection for the gates in a combinatorial circuit which uses the problem of finding a shortest path in an oriented acyclic graph for making certain updates between any two successive iterations. For this NP-hard problem, we give an approximation algorithm.
Related Topics
Physical Sciences and Engineering
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