Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications

In this work, gate-stack based junctionless Si-nanotube (JLSiNT) FET is studied to investigate the effect of high-K gate dielectric material in-conjunction with interfacial layer thickness (TI) and outer gate length (Lg) on analog/RF figures of merit (FOM) of the device. With the use of high-K gate dielectric intrinsic dc gain (AV), cut-off frequency (fT), and maximum oscillation frequency (fMAX) degrades. It is observed that the degradation in analog/RF performance when high-K gate dielectrics are used, can be improved by taking higher TI. Furthermore, it is also observed that by using optimal TI (0.7 nm), the variation in ΔAV (AV(K=3.9) - AV(K=40)), ΔfT (fT(K=3.9) - fT(K=40)), and ΔfMAX (fMAX(K=3.9) - fMAX(K=40)) FOMs are almost invariant when outer gate length (Lg) is scaled down from 30 nm to 15 nm. Therefore, it is pertinent to consider higher interfacial layer thickness (~0.7 nm) and lower outer gate length (~ 15 nm) while designing gate-stack based JLSiNT-FET for analog/RF applications.