Investigation into the capabilities of Hall cells integrated in a non-fully depleted SOI CMOS technological process

The behaviour of SOI Hall cells integrated in a non-fully depleted SOI (“Silicon-On-Insulator”) CMOS technology is investigated, with an emphasis on the study of their main parameters. To meet these objectives, a particular optimum structure has been designed, integrated and subsequently analyzed. The performance evaluation of this Hall cell is carried out by means of both a three-dimensional physical model and measurements. The Hall voltage, electrostatic potential distribution and sensitivity have all been evaluated. In addition, the Hall mobility has been studied through simulations. In order to complete the performance assessment of the Hall cells studied, experimental results for the offset and variation of the sensitivity with the temperature are also provided.