| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 713885 | IFAC Proceedings Volumes | 2013 | 4 Pages |
Abstract
A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on replacement of the state register by a state counter. The main di_erence form already known methods is that the counter increases its state during conditional and unconditional transitions. An example of application of proposed methods is given.
Related Topics
Physical Sciences and Engineering
Engineering
Computational Mechanics
