The optimization of parallel multiplication

These article presents a solution of the synthesis of parallel multiplication systems with the alternative – mutually excluding results the addition of partial products. The paper uses “n:m reducers” to determine the sums of bits of partial products for parallel multipliers in the diagram of Wallace tree. The elaboration refers to the solution for multiplying numbers of 8 bits, but it can be enlarged for 16 and 32 bits. The proposed solution gives the opportunity to use the probability of conditional significant partial products and faster service – fewer logic levels for special cases of multiplication related to the specific values of the sums of partial product bits.