| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 713899 | IFAC Proceedings Volumes | 2013 | 6 Pages |
Abstract
The method is proposed for reduction of hardware amount in logic circuit of Moore finite state machine implemented with PLAs. It is based on using classes of pseudoequivalent states. Each a class corresponds to a unique state of equivalent Mealy FSM. In this method the next state code is represented as a concatenation of codes for class of pseudoequivalent states and collection of output variables. Such an approach allows the elimination of dependence among states and output variables.
Related Topics
Physical Sciences and Engineering
Engineering
Computational Mechanics
