Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40Â nm technology

In this paper, MOSFET layout-dependent gate-around capacitance which include gate-to-source/drain fringing capacitance (Cf) separated from gate-to-contact capacitance (Cco), has been extracted in SPICE model. This work focuses on layout-dependent-effect (LDE) in AC characteristics such as Cf and Cco of MOSFET. To separate Cf and Cco, novel test structures have been designed and fabricated by 40 nm process. According to the silicon data, the apparent variation of Cf with contact to poly space (CPS) and contact to contact space (CCS) has been modeled and exactly extracted. The errors between silicon data and simulation are mainly under 5%. The extraction and modeling of the layout-dependent Cf in this work will contribute high accuracy for digital and RF circuit simulation in advanced CMOS node.