| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 7151101 | Solid-State Electronics | 2012 | 7 Pages |
Abstract
⺠We evaluate parasitic capacitances for each double gate structure. ⺠Planar structure optimization are proposed, such as internal spacers. ⺠We prove that optimized planar DG present higher circuit performance than FinFET.
Related Topics
Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
J. Lacord, J.-L. Huguenin, S. Monfray, R. Coquand, T. Skotnicki, G. Ghibaudo, F. Boeuf,