Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
7151240 | Solid-State Electronics | 2011 | 7 Pages |
Abstract
The potential of strained DOTFET technology is demonstrated. This technology uses a SiGe island as a stressor for a Si capping layer, into which the transistor channel is integrated. The structure information of fabricated samples is extracted from atomic force microscopy (AFM) measurements. Strain on the upper surface of a 30Â nm thick Si layer is in the range of 0.7%, as supported by finite element calculations. The Ge content in the SiGe island is 30% on average, showing an increase towards the top of the island. Based on the extracted structure information, three-dimensional strain profiles are calculated and device simulations are performed. Up to 15% enhancement of the NMOS saturation current is predicted.
Keywords
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Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
Johann Cervenka, Hans Kosina, Siegfried Selberherr, Jianjun Zhang, Nina Hrauda, Julian Stangl, Guenther Bauer, Guglielmo Vastola, Anna Marzegalli, Francesco Montalenti, Leo Miglio,