Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
7151285 | Solid-State Electronics | 2011 | 7 Pages |
Abstract
A simple approach for manufacturing quasi-planar bulk MOSFET structures is demonstrated and shown to be effective not only for improving device performance but also for reducing variation in 6T-SRAM read and write margins, in an early 28Â nm CMOS technology. With optimization of the pocket implant doses, voltage scaling is facilitated. Since its benefits increase with decreasing channel width, quasi-planar bulk MOSFET technology should be advantageous for future CMOS technology generations (22Â nm and beyond).
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Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
Changhwan Shin, Chen Hua Tsai, Mei Hsuan Wu, Chung Fu Chang, You Ren Liu, Chih Yang Kao, Guan Shyan Lin, Kai Ling Chiu, Chuan-Shian Fu, Cheng-tzung Tsai, Chia Wen Liang, Borivoje NikoliÄ, Tsu-Jae King Liu,