Substrate bias dependency of sense margin and retention in bulk FinFET 1T-DRAM cells

► The substrate bias can be used to optimize the retention and sense margin in bulk FinFET 1T-DRAM cells. ► Retention times as high as 2 s with a sense margin of 100 μA can be achieved for bulk FinFET memory cells with WFIN = 20 nm when a substrate bias of −0.5 V is used. ► Next to the substrate bias, the read-out biasing will impact the memory cell performance.