| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 7151312 | Solid-State Electronics | 2011 | 6 Pages |
Abstract
⺠We report a simulation study on a device exploiting combined band-to-band and barrier tunneling mechanisms. ⺠This device overcomes the low current drive of conventional Tunnel FETs and has a sub-60 mV/decade subthreshold slope. ⺠The new switch is a gated m-i-n+ structure which has an ultra-thin dielectric between metal source and silicon channel. ⺠We evaluate the impact of the tunneling layer thickness on performances and compare single and double gate architectures. ⺠We assess the impact of device gate length scaling: subthreshold slope and ON current improve at smaller gate lengths.
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Authors
Livio Lattanzio, Arnab Biswas, Luca De Michielis, Adrian M. Ionescu,