Discrete Control for Reconfigurable FPGA-based Embedded Systems*

This work presents an application of discrete controller synthesis (DCS) techniques to a class of dynamically reconfigurable embedded computing systems, and contributes to the general approach of control for feedback computing. We propose a general model for applications defined as data-flow graphs of computing tasks, and target execution architectures that are dynamically partially reconfigurable Field Programmable Gate Arrays (FPGAs). We define our model in terms of parallel automata. Then, we encode relevant scheduling and control requirements in terms of a DCS problem w.r.t. multiple constraints and objectives. We take into account the system reconfiguration overhead, and the resulting controller is able to make decisions by foreseeing their impact on future requests. We validate our approach by using the BZR programming language and Sigali tool for modelling and simulations, with a video processing system implementation on a specific FPGA platform.