Stream header decoder and context-adaptive variable-length decoder hardware module for H.264/AVC codec

This paper describes the implementation of stream header decoder and context-adaptive variable-length decoder in conformity with the H.264/AVC standard. This module is able to decode headers of syntax elements and to decode blocks of transform coefficients coded using context-adaptive variable-length coder. The designed module is synthesized based for FPGA and ASIC technologies and verified with the reference model JM in version 16. The implementation results shows that the architecture can work at 100 MHz for FPGA Stratix 2 devices and can support HDTV in real time.