A High Level Modeling Approach for Reconfigurable System Architecting

Reconfigurable computing architectures have recently emerged as potential answers to satisfy new requirements imposed on real-time embedded system design. To efficiently cope with resulting increased design complexity, innovative codesign methods are needed to consider the reconfiguration property in the whole system design process. In this paper, we present a high level modeling approach for hardware resource reconfiguration mechanisms analysis. The proposed approach makes possible to explore and size heterogeneous and reconfigurable architectures according to expected system performances.