| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 720945 | IFAC Proceedings Volumes | 2009 | 6 Pages |
Abstract
The paper presents an analysis of square wave frequency multiplying process and a synthesis of the cascade multiplying device (by positive real number) which consists of delay units and simple logic devices. The Walsh functions are used for describing of frequency multiplier operation. On this base the multiplying error analysis was elaborated.
Related Topics
Physical Sciences and Engineering
Engineering
Computational Mechanics
