| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 721423 | IFAC Proceedings Volumes | 2006 | 6 Pages |
Abstract
Hardware Embedded DEductive Fault Simulation (HEDEFS) is a hardware-software realization of a deductively-parallel topological method of faults modeling. The method uses ad hoc technology of the analysis of converging branching, back-word modeling of faults simulation, and transformation of testable circuits; and is oriented on handling of digital circuits with big dimension represented on gate or RT description levels. Structural hardware solutions for realization of the method are presented at an estimation of quality of generated tests.
Keywords
Related Topics
Physical Sciences and Engineering
Engineering
Computational Mechanics
Authors
Vladimir Hahanov, Hassan Kteaman, Wade Ghribi, Elena Fomina,