HIERARCHICAL SELF TEST FOR SOCS INCLUDING LOGIC AND INTERCONNECTS

Systems on a Chip (SoCs) typically consist of several processor devices, embedded memory blocks, application-specific logic blocks and complex interconnects. While embedded memory blocks are mostly equipped with built-in self test (BIST) capabilities, test methods for processors, logic blocks and interconnects are still topics of intensive research. Beyond production testing, SoCs in safety-critical applications also need built-in self test capabilities, which work independently from external control hardware. A HW / SW –based self test scheme can facilitate self test in the field of application making efficient use of structures for production test and can even supplement production test, e.g. for internal interconnects. The paper describes the architecture, cost and limitations.