PETRI NET DECOMPOSITION APPROACH FOR PARTIAL RECONFIGURATION OF LOGIC CONTROLLERS

In the paper design method of Reprogrammable Logic Controllers oriented on partial reconfiguration is presented. The Controller is specified by Interpreted Petri net. The Petri net model is decomposed onto a set of State Machine (SM) subnets. Each subnet is modelled using Verilog, and then all subnets are implemented using Field Programmable Gate Arrays (FPGAs). The novel capability of the method is the opportunity for dynamic change of the FPGA configuration with a portion of the original bitstream. Such approach is necessary when a transmission channel for a new configuration is a bottleneck.