State Machine description oriented towards effective usage of vendor-independent synthesis tools

The paper concerns the problem of Finite State Machine (FSM) description in Hardware Description Languages (HDL), and effective usage of vendor-independent synthesis tools, including academic software, in synthesis dedicated for Complex Programmable Logic Devices (CPLD-s). The authors propose an alternative method of porting a design from a vendor-independent synthesis tool to a vendor system, for completing the implementation stage. The method utilises a special style of VHDL modelling, so the description is universal and comprehendible to a human. Efficiency of the method was verified by experiments carried out using academic software, and leading commercial tools.