Hardware implementation of the MD5 algorithm.

The paper presents a hardware implementation of the MD5 hash generator. The generator comprises MD5 processing unit, data exchange interface and memory block for storing input messages. A general concept and implementation of the MD5 generator modules is described. Presented solution is based on the finite state machines; its performance is compared with other MD5 implementations. The MD5 generator has been modelled using VHDL and targeted to a Xilinx Spartan-3E device. Unlike compared implementations, which are mainly designated for Internet applications, this module is optimised to work as a part of video based device for measuring road traffic parameters. The MD5 generator is responsible for signing video stream captured in real time.