Strained silicon — the key to sub-45 nm CMOS

Strain techniques, such as incorporating SiGe, should boost performance in future generations of CMOS silicon transistors without the need to radically scale transistor dimensions. Although strain is already used for some technology nodes, more knowledge needs to be developed, e.g. on the relationship between strain, carrier mobility and device performance, to employ it further. Also, combination with other options, such as MuGFETs, high-k materials and metal gates, is being considered.