Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
724819 | Journal of Electrostatics | 2006 | 16 Pages |
Abstract
Design automation tools for ESD are described that ensure robust protection at both the cell and chip level in a high-volume, highly automated ASIC design system. The Charged Device Model (CDM) failure modes discovered in the 130 nm technology are described, and the design automation tools that were implemented to prevent these failures are presented. There are three primary components: Design rule checking for ESD; transient CDM simulations on extracted net lists; and analysis of chip-level power supply net resistances.
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Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
Ciaran J. Brennan, Joseph Kozhaya, Robert Proctor, Jeffrey Sloan, Shunhua Chang, James Sundquist, Terry Lowe, David Picozzi,