| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 725012 | The Journal of China Universities of Posts and Telecommunications | 2013 | 7 Pages |
Abstract
Serial RapidIO (SRIO) is an emerging high-performance interconnection technology for embedded systems. Protections for SRIO packets are provided by the cyclic redundancy check (CRC). In this paper, an improved CRC receiving controller with 64-bit internal data width is proposed. Equivalent judgment logics are adopted in the aims of reducing the number of CRC generators. The resource consumption and power dissipation can be saved meanwhile the frequency requirement can still be met. By comparison to conventional structures, the proposed scheme can achieve better performances. Therefore, this improved receiving controller is considered applicable in high-performance SRIO interconnections.
Related Topics
Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
