Time-to-digital converters based on event-driven successive charge redistribution: A theoretical approach

Due to reduction of supply voltage and improving the time resolution with continued down scaling of CMOS technology, encoding signal values in the time domain has become a technique of increasing importance in modern signal processing. Time encoding is proposed to be an underlying principle and a general postulate of Time-Mode Signal Processing (TMSP). In particular, time encoding is used in the asynchronous analog-to-digital conversion (A-ADC) to encode the asynchronous sequence of time intervals that represent signal amplitude values. In the paper, a new method of time-to-digital conversion (TDC) is proposed where the discretized time interval is first converted to the corresponding charge packet, and next processed in the charge domain by event-driven successive charge redistribution. The proposed circuit configuration is extremely simple and contains only a binary-weighted capacitor array, one or two current sources, a group of controlled switches, two comparators and an asynchronous state machine. The TDC architecture is scalable, self-timed and does contain neither a clock nor a digital-to-analog converter. The development of the successive redistribution TDC makes possible removing the clock not only from time encoding block but also from the time-to-digital converter in A-ADCs.

► We propose a new time-to-digital converter with successive charge redistribution. ► The time-to-digital converter is clockless and self-timed. ► The time-to-digital conversion adapts the binary search principle in time domain. ► The number of state transitions per conversion cycle is minimized.