Fast estimation of ADC nonlinearities using the Sinewave Histogram Test

The Sinewave Histogram Test (SHT) is a widely used standard technique to estimate the threshold voltages and the Integral NonLinearity (INL) pattern of Analog-to-Digital Converters (ADCs). The main drawback of the SHT is that, for a given target accuracy, the number of test samples as well as the testing time tend to increase exponentially as the resolution of the converter grows. The strategy described in this paper still relies on the SHT, but it enables a major reduction in testing time without affecting estimator accuracy provided that the INL pattern exhibits prevailingly a low code frequency content. This result can be achieved simply by suitably filtering the INL pattern obtained using a standard SHT over a reduced amount of test samples. After being justified theoretically, the proposed solution is validated by means of both simulations and experimental evidences.