CMOS image sensor employing 3.3 V 12 bit 6.3 MS/s pipelined ADC

This paper presents an implementation of a conventional 256 × 256 CMOS image sensor (CIS) system with on-chip 12 bit, 6.3 MS/s CMOS pipelined analog-to-digital converter (ADC). The test chip has been implemented in 0.35 μm 2P4M process, operated by a 3.3 V supply and its total power consumption is only 50 mW with maximum DNL of −0.8 LSB and maximum INL of ±4.2 LSB under 6.3 MS/s. The total area of the prototype is 12 mm2, and the core area of ADC is only 18% of the total area. System architecture and operation are discussed and measurements from a test chip are showed.