Impact of metal silicide layout covering source/drain diffusion region on minimization of parasitic resistance of triple-gate SOI MOSFET and proposal of practical design guideline

This paper describes the impact of silicide layout in the source/drain region on the parasitic resistance of the multiple-fin triple-gate (TG) SOI MOSFET. For multiple-fin TG SOI MOSFET’s with narrow source and drain regions (∼40 nm), it is demonstrated that the Π-shape layout with a thin silicide film results in the lowest parasitic resistance, and that a deep ‘localized-silicide’ layout also contributes to a low parasitic resistance. On the other hand, for multiple-fin TG SOI MOSFET’s with wide source and drain regions (∼80 nm), it is shown that a deep ‘localized-silicide’ layout results in the lowest parasitic resistance. However, for a very narrow source and drain regions (∼10 nm), it is also strongly suggested that a new technique is needed to drastically reduce the parasitic resistance of source and drain diffusion regions in future sub-10-nm-long channel TG SOI MOSFET’s.Simulation results strongly indicate that both the silicide/Si contact area and the cross-sectional area of remaining Si region should be as large as possible to yield a low parasitic resistance; a practical design guideline for silicide layout is proposed on the basis of the important role of silicide/Si contact resistance and its validity is confirmed.