Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
747462 | Solid-State Electronics | 2009 | 6 Pages |
Abstract
Ultra-low off current (Ioff < 1 pA/μm) “silicon on thin buried oxide (SOTB)” CMOSFETs were developed using 65-nm technology. The off current of SOTB CMOSFETs was studied and gate-induced drain leakage (GIDL) was adequately reduced by controlling the gate-overlap length. A back-gate bias in a SOTB scheme was demonstrated, and the inverter delay was compared with conventional low-standby-power bulk CMOSFETs. We show small variation in SOTB devices and estimate the standby leakage of a 1-M bit SRAM. The half threshold voltage standard deviation (σVth) of SOTB devices corresponds to a reduction in the standby leakage current of less than half. The ultra-low off current with a small variation also further reduces the standby leakage.
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Authors
T. Ishigaki, R. Tsuchiya, Y. Morita, H. Yoshimoto, N. Sugii, T. Iwamatsu, H. Oda, Y. Inoue, T. Ohtou, T. Hiramoto, S. Kimura,