Numerical modeling of RF noise in scaled MOS devices

A new approach to numerical noise simulation for MOSFETs based on bipolar 2D drift-diffusion and hydrodynamic models is presented, where the hierarchical approach for volume transport has been extended to the case of inversion layers. With the new models RF noise in scaled NMOSFETs is investigated and simulation results are compared to measurements for a 180 nm technology. Important noise quantities like the drain and gate excess noise factors and the gate/drain correlation coefficient are discussed in detail. It is found that the drain excess noise factor increases only moderately in short channel devices down to 70 nm gate length independent of the device type (bulk, SOI or double gate). Although the gate excess noise factor increases significantly at shorter gate lengths, the minimum noise figure strongly decreases predicting superior noise performance for sub-100 nm devices. Furthermore, the impact of the substrate resistance on RF noise is discussed including bias conditions near breakdown, where carrier generation by impact ionization becomes significant.