Investigation of process-induced performance variability and optimization of the 10 nm technology node Si bulk FinFETs

•We report the process-induced performance variability in 10 nm bulk n/p-FinFETs.•In single-fin, Wfin and Lg are the most important in performance variablity.•In multi-fins, the absolute gm value increase is more important than variability.•In AC, Cpara of 3D metal interconnect is rather critical than that of device itself.•We identify key factors and strategies for mitigating variability.

we propose a process and device design strategy for Lg = 14 nm Si bulk n/p-FinFETs based on the effects of process-induced geometry variability on device performance. A calibrated TCAD simulation was used to design and optimize structures and these were also tested under various process split conditions. By comparing the I–V data from process-changed devices with nominal CMOS, relationships between process- induced geometry variation and device performance were investigated and analyzed. Moreover a DC/RF compact model was executed to observe the geometry variability effects on ring oscillator and RF applications. Finally key circuit design factors to mitigate process variability are suggested.