Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
747804 | Solid-State Electronics | 2013 | 7 Pages |
This study explores the detailed charge-trapping behaviors of silicon–oxide–nitride–oxide–silicon (SONOS) type devices with various charge trapping layers, including silicon oxy-nitride (SiON), nitrogen-rich silicon nitride (N-rich SIN), typical SIN (STD SIN), and silicon-rich SIN (Si-rich SIN) by using our recently developed gate-sensing and channel-sensing (GSCS) transient analysis method. Our results clearly demonstrate that the charge trap efficiency, electron hopping capability, and the movement of electron centroid inside the SIN decrease with reducing the Si content from Si-rich to N-rich SIN while SiON shows the worst performances among these trapping layers, which is strongly correlated to material itself and independent of external factors. Negative gate voltage (−Vg) stressing test also displays the same phenomenon and suggests that the charges mainly trapped at the bottom portion for SiON, and move to the top portion as increasing the Si content from N-rich to Si-rich SIN.
► Charge-trap behaviors of SONOS were studied by gate-sense/channel-sense method. ► Reducing Si ion of SIN would degrade charge trap efficiency and hop capability. ► SiON shows the worst performances in charge trap efficiency and hop capability. ► Charges trapped at bottom and move to top as increasing Si ion of SIN. ► For SiON, charges mainly trapped at the bottom portion.