Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (Wtop_eff) was investigated, experimentally. As decreasing Wtop_eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (Cgc–Vg), resulting in a noticeable change in the effective mobility (μeff) behavior from that in wide JLT devices, an increase of the threshold voltage (Vth), while the flat-band voltage (Vfb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure.

► Electrical behavior of JLT devices depending on width variation was investigated. ► As decreasing width, sidewall gate (SG) effect is reinforced. ► These cause that the shoulder shape on the normalized Cgc curve is shrunk. ► A noticeable change in the μeff behavoir and the up-shifted Vth are observed. ► Experimental results regarding the SG effects were proved by 2D numerical simulation.