MOSFET gate dimension dependent drain and source leakage modeling by standard SPICE models

The leakage current in standard MOSFET models (BSIM3/BSIM4) is typically modeled by drain–bulk and source–bulk diodes. This modeling method does not consider the impact of several parasitic bipolar devices. For the accurate modeling the impact of the following bipolar transistors has to be considered: a lateral bipolar transistor drain–bulk–source, a vertical bipolar transistor drain–bulk-substrate (only in isolated structures), and a vertical bipolar transistor source–bulk-substrate (only in isolated structures). For example, the drain or source leakage as a function of gate length cannot be modeled without the scalable parasitic bipolar devices. This contribution demonstrates the structure of a proposed macro model, implemented scalability (in most cases nonlinear), developed scaling equations, and physical explanation of this scaling.Finally, the comparison of measured data vs. simulation is presented in order to confirm the model validity. This model improvement solves not only leakage current scaling, but it also accounts for additional parasitic bipolar effects, such as current injection to the substrate.

► The source/drain leakage modeling has been proposed by adding several parasitic BJTs. ► The proposed scaling equations makes the higher geometry accuracy. ► These models improvements also accounts for additional parasitic bipolar effects. ► Added BJTs are not active when MOSFET operates in the standard regime in ON state.