Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
747902 | Solid-State Electronics | 2011 | 5 Pages |
A new stacked-nanowire device is proposed for 3-dimensional (3D) NAND flash memory application. Two single-crystalline Si nanowires are stacked in vertical direction using epitaxially grown SiGe/Si/SiGe/Si/SiGe layers on a Si substrate. Damascene gate process is adopted to make the gate-all-around (GAA) cell structure. Next to the gate, side-gate is made and device characteristics are controlled by the side-gate operations. By forming the virtual source/drain using the fringing field from the side-gate, short channel effect is effectively suppressed. Array design is also investigated for 3D NAND flash memory application.
► We propose a multi-nanowire device with virtual source/drain. ► We measured the fabricated device showing an effective side-gate operation. ► We also carried out a measurement of memory operation in the fabricated device. ► We designed a 3D array using a connection gate (CG) and layer select lines (LSL).