Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. 1 × 1019 cm−3 n-type channel doping, 5–20 nm Si nanowire width together with 2 nm SiO2 gate oxide thickness were used in the quasistationary TCAD device simulations of 100 nm long channel devices (VDS = 100 mV, T = 300 K). All the extensive studies were performed in strong accumulation regime, as a first step, using a constant electron mobility model (100 cm2/V s). The effects of non-uniform electron density due to corners and quantum confinement effects are investigated. Suppressing the bias-dependency of various key MOSFET parameters e.g. series resistance, by contact engineering, and the product of channel width and gate-channel capacitance, CWeff, by rounding the sharp corners, to improve the accuracy of mobility extraction in strong accumulation is addressed in details. A significant bias-dependent series resistance modulation is reported in GAA Si nanowire junctionless nMOSFETs, leading to a significant electron mobility extraction inaccuracy of ∼50% in strong accumulation regime.