Progress in Z2-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage

In this paper, we extend our studies on the use of zero impact ionization and zero subthreshold swing field-effect-transistor (Z2-FET) as a capacitor-less one-transistor dynamic random access memory (1T-DRAM) through both experiment and TCAD simulation. The data retention time is measured as a function of biasing, temperature and device dimensions, leading to a simple predictive model. An alternative writing method using the source MOSFET is presented, which is potentially more compatible with the conventional DRAM array design. The operation of a Z2-FET memory array is discussed, in which the write and read signals are adapted from the single cell to achieve selective operation. Finally, we present simulations demonstrating that the Z2-FET can be used to store multiple bits thanks to the charges on both the top and bottom gate capacitors.

► One-transistor DRAM based on Z2-FET sharp-switching device. ► Long retention time (> 1 s) at low VDD supported by simple modeling. ► Biasing sequence compatible with selective bit addressing in a DRAM array. ► Dual bit storage in a non-overlapping gate structure scalable to 25 nm.